This invention is generally concerned with digital-to-analogue converters and more particularly relates to techniques for reducing signal dependent loading of reference voltage sources used by these converters.
Digital-analogue conversion based on converting a delta-sigma digital representation of a signal into an analogue waveform is now a commonplace technique. In a simple delta-sigma digital-to-analogue converter a string of pulses is generated, with a pulse density dependent upon the digital value to be converted, and low-pass filtered. The technique is prevalent in many high-volume application areas, for example digital audio, where several channels of high quality relatively low frequency (audio frequency) signals are required. High quality in this context typically implies xe2x88x92100 dB THD (Total Harmonic Distortion) and 100 dB SNR (Signal to Noise Ratio). However, in such high-volume markets manufacturing cost is also very important.
In general, a digital-to-analogue converter requires positive and negative reference voltages to define the amplitude of the output signal. A digital-to-analogue converter draws some current from these reference voltage ports, and this current will generally be signal dependent.
These reference voltages are typically generated from a source of low but non-zero output impedance, for example by a power supply or buffer with a decoupling capacitor. The source will have a finite ESR (Equivalent Series Resistance), and there will be additional resistance between the source, the decoupling and the device due to the effects of resistive PCB tracking, package lead resistance, and bond wire resistance.
The result is that any signal-dependent current drawn by the DAC from the references causes a signal-dependent voltage ripple to appear on the reference voltages actually applied to the DAC. Since the DAC output signal is proportional to the reference voltage, this multiplies the ideal digital-to-analogue converter output by this ripple. The consequent modulation of the output signal is apparent as signal distortion, for example, generating harmonic distortion components with a sine wave signal.
Furthermore in a stereo or multi-channel system it is often uneconomic to supply a digital-to-analogue converter for each channel with a separate voltage reference supply, or even separate decoupling, PCB traces, or integrated circuit pins. In these situations the reference ripple caused by one channel""s DAC can appear on the reference voltage for other DACs, modulating the outputs of these other DACs as well as its own output.
This invention described herein is directed to digital-to-analogue converter circuits intended to reduce or eliminate signal dependent reference currents. A digital-to-analogue converter design for which the reference currents are substantially independent of output signal should be capable of lower distortion for a given source impedance. Alternatively, for a given acceptable level of performance, the digital-to-analogue converter should be more tolerant of source impedance, so allowing a design engineer to reduce costs by specifying fewer or cheaper, lower quality external components.
Many delta-sigma digital-to-analogue converters use switched-capacitor techniques. FIG. 1 shows an example of a simple switched-capacitor DAC 100 suitable for use in a delta-sigma DAC system.
An operational amplifier 102 has a non-inverting input connected to a constant voltage Vmid 118, typically ground. Operational amplifier 102 has an output 120 providing an output voltage Vout and a feedback capacitor Cf 104 is connected between the output and an inverting input of the operational amplifier. A second capacitor C2106 is switchably connected across feedback capacitor 104 by means of switches 108 and 110. Switch 108 allows one plate of capacitor 106 to be connected either to Cf 104 or to a positive reference voltage VP 112 or a negative reference voltage VN 114. Switch 110 allows the other plate of capacitor 106 to be connected either to feedback capacitor 104 or to a second constant voltage, Vmid2 116.
In operation switches 108 and 110 are controlled by a clock generator (not shown in FIG. 1) providing two clock phases Phi1200 and Phi2202, as shown in FIG. 2. Each of these clock signals comprises a charge phase 204 during which capacitor C2106 is charged and a dump phase 206 during which the charge on capacitor C2106 is shared with or dumped to the feedback capacitor Cf 104. As can be seen from FIG. 2 Phi1200 controls the charging phase and Phi2202 controls the dump phase.
In more detail, during the charging phase Phi1 (200, 204) capacitor C2 is charged, with Vmid2 (generally the same voltage as Vmid) applied to one terminal and VP or VN applied to the other terminal. Typically values of VP 112 and VN 114 are +3V and xe2x88x923V respectively, with respect to Vmid 118. The choice of VP or VN for any particular cycle is defined by a digital delta-sigma signal applied to switch 108 during this charging phase Phi1. During the dump phase, Phi2 (202, 206), C2 is disconnected from VP, VN and Vmid2 and connected in parallel with the op amp feedback capacitor Cf 104.
Typically C2106 is much smaller than the op amp feedback capacitor Cf 104. The left-hand side of C2 is switched between a voltage equal to Vmid 118 (since the inverting terminal of op amp 102 is a virtual earth, that is it is at substantially the same voltage as the non-inverting terminal) and Vmid2. Assume for simplicity that as usual Vmid2=Vmid. Then if VP rather than VN is applied to the other end of C2 during Phi1200 for many consecutive clock cycles, the output Vout 120 will converge to equal VP 112, to achieve a steady state in which both the left-hand side and the right-hand side of C2106 are switched between equal voltages each cycle. Similarly if VN 114 is applied each cycle, Vout will converge to VN 114. If VP and VN are each applied half the time, the output 120 will be the average of VP and VN. In general for a VP:VN duty cycle of m: (1xe2x88x92m), the steady-state output will be given by Vout=m*VP+(1xe2x88x92m)*VN. In this context xe2x80x9cduty cyclexe2x80x9d should be understood as the fraction, proportion or ratio of the number of connections to VP to the number of connections to VN, for example measured in clock cycles.
The duty cycle is controlled by a digital delta-sigma signal to alternately connect C2106 to VP and VN to provide the required output voltage 120. This output voltage 120 will vary from VP to VN according to the duty cycle applied. Thus, in effect, the DAC circuit may be considered as having a gain from the voltages (112 and 114) applied to the switched capacitor to the output 102 defined by (Vout,maxxe2x88x92Vout,min)/(VPxe2x88x92VN) of substantially unity. The skilled person will recognise that the gain of circuit 100 may be adjusted, for example, by connecting a voltage divider to output 120 and taking the voltage for capacitor Cf 104 from a tap point on this divider, for example to provide a gain of 2. However typically the circuit will have a relatively low gain, for example less than 10 and more typically less than 3. This also applies to the DAC circuits which are described later.
The applicant has recognised that the above-described prior art DAC circuit suffers from a problem associated with signal-dependent loading of reference voltage sources for voltages VP 112 and VN 114. The effects of signal-dependent loading of reference voltage supplies are known in the context of other circuits, but it has not previously been recognised that switched capacitor DAC circuits of the type shown in FIG. 1, in which a charge-sharing capacitor connected in parallel with a feedback capacitor is alternately connected to both positive and negative reference voltage sources, can also suffer from this problem. Thus, for example, U.S. Pat. No. 5,790,064 is concerned with mitigating the effects of signal-dependant reference source loading for a switched capacitor integrator, which has theoretically infinite gain at dc and which does not operate on the principle of charge sharing, instead dumping charge into an input of an operational amplifier which in turn drives an integration capacitor. Other switched capacitor integrators are described in U.S. Pat. No. 5,703,589 and FR 2,666,708. The integrators of these prior art circuits all form part of analogue-to-digital converter circuits and are not intended or suitable for use as high quality digital-to-analogue converters. Background prior art can be found in U.S. Pat. Nos. 4,896,156, 4,994,805, EP 0 450 951 (and U.S. Pat. No. 5,148,167), U.S. Pat. Nos. 6,081,218, 6,337,647, EP 1130 784 and in IEEE Solid State Circuit Conference (ISSCC) 2000 paper xe2x80x9cA 120 dB Multi-bit SC Audio DAC with Second Order Noise Shapingxe2x80x9d, J Rhode, Xue-Mei Gong et al., pages 344-5.
The manner in which signal-dependent reference source loading arises in the DAC circuit of FIG. 1 can be seen by considering the charge taken from VP and VN averaged over many cycles. For the above m: (1xe2x88x92m) duty cycle, and assuming for simplicity that C2 less than  less than Cf, so that cycle-by-cycle ripple on Vout is small, for VP this is given by:                               m          *                      (                                          V                P                            -                              V                out                                      )                    *          C2                =                  xe2x80x83                ⁢                  m          *                      (                                          V                P                            -                              (                                                      m                    *                                          V                      P                                                        +                                                            (                                              1                        -                        m                                            )                                        *                                          V                      N                                                                      )                                      )                    *          C2                                        =                  xe2x80x83                ⁢                  m          *                      (                          1              -              m                        )                    *                      (                                          V                P                            -                              V                N                                      )                    *          C2                    
This has a parabolic dependence on m, with zeros at m=0 and m=1, and a maximum of 0.25*(VPxe2x88x92VN)*C2 at m=0.5. VN shows a similar dependence.
FIG. 3 shows a digital-to-analogue converter 300 with a differential voltage output 120a, b, based upon the circuit of FIG. 1. As can be seen from inspection of FIG. 3, the differential DAC 300 comprises two similar but mirrored circuits 100a, 100b, each corresponding to DAC 100. The positive differential signal processing circuit portion 100a generates a positive output Vout+120a and the negative differential signal processing portion 100b generates a negative voltage output Voutxe2x88x92120b. Likewise the positive circuit portion 100a is coupled to first reference voltage supplies VP+112a and VN+114a and the negative circuit portion 100b is coupled to second reference voltage supplies VPxe2x88x92112b and VNxe2x88x92114b. 
Preferably VP+112a and VPxe2x88x921112b are supplied from a common positive reference voltage source and VN+114a and VNxe2x88x92114b are supplied from a common negative reference voltage source. Thus preferably VP+ and VPxe2x88x92 are at the same voltage and the VN+ and the VNxe2x88x92 are at the same voltage. As can be seen C2+106a is switched to references VP+112a and VN+114a and C2xe2x88x92106b is switched to references VPxe2x88x92112b and VNxe2x88x92114b. Voltages Vmid2+116a and Vmid2xe2x88x92116b preferably have the same value, preferably the value of Vmid 118, typically ground. Preferably feedback capacitors 104a, b and switched capacitors 106a, b have the same value and op amps 102a and 102b are matched. Op amps 102a, b may comprise a single differential-input, differential-output op amp. These same comments also apply to the later described differential DAC circuits.
Continuing to refer to FIG. 3, in operation, whenever VP+ is chosen to charge C2+ VNxe2x88x92 is selected to charge C2xe2x88x92. Thus by symmetry one can write Voutxe2x88x92=m*VNxe2x88x92+(1xe2x88x92m)*VPxe2x88x92. (When m=0.5, Vout+=Voutxe2x88x92=(VP+VN)/2. As m varies Vout+ and Voutxe2x88x92 will swing in equal amplitude but opposite polarities about this common-mode voltage.)
The average charge taken from VP+ will be as above:                               m          *                      (                                          V                P                +                            -                              V                out                +                                      )                    *                      C2            +                          =                  xe2x80x83                ⁢                  m          *                      (                                          V                P                +                            -                              (                                                      m                    *                                          V                      P                      +                                                        +                                                            (                                              1                        -                        m                                            )                                        *                                          V                      N                      +                                                                      )                                      )                    *          C2                                        =                  xe2x80x83                ⁢                  m          *                      (                          1              -              m                        )                    *                      (                                          V                P                +                            -                              V                N                +                                      )                    *                                    C2              +                        .                              
The average charge taken from VPxe2x88x92 will be:                                           (                          1              -              m                        )                    *                      (                                          V                P                -                            -                              V                out                -                                      )                    *                      C2            -                          =                  xe2x80x83                ⁢                              (                          1              -              m                        )                    *                      (                                          V                P                -                            -                              m                *                                  V                  N                  -                                            -                                                (                                      1                    -                    m                                    )                                *                                  V                  P                  -                                                      )                    *                      C2            -                                                  =                  xe2x80x83                ⁢                              (                          1              -              m                        )                    *          m          *                      (                                          V                P                -                            -                              V                N                -                                      )                    *                      C2            -                              
Thus the total charge taken from VP (that is VP+ and VPxe2x88x92) is 2*m*(1xe2x88x92m)*(VPxe2x88x92VN)*C2. This is just double the charge of the single-sided implementation, as might be surmised by the symmetries of the circuit. Again the function is parabolic, with a minimum of zero (for m=0 or 1) and a maximum of 0.5*(VPxe2x88x92VN)*C2.
To take an example, consider a case where VP=+3V, VN=xe2x88x923V, and C2=10 pF. Assuming the circuit is clocked at 10 MHz, this will give rise to a current varying from zero to 0.5*(+3Vxe2x88x92(xe2x88x923V))*10 pF*10 MHz=300 xcexcA drawn from VP and VN depending on the low-frequency level of the output signal Vout. If the equivalent source impedance of the sources of VP and VN are 1 ohm each, this will give a modulation of (VPxe2x88x92VN) of 0.6 m Vpkxe2x88x92pk., that is 0.1% of (VPxe2x88x92VN). This will modulate the output signal by a similar amount (as with a multiplying DAC) and is a gross effect in a system aimed at typically xe2x88x92100 dB (0.001%) THD.
There is therefore a need for charge-sharing, switched capacitor DAC circuits which exhibit reduced signal-dependent loading of reference sources.
According to a first aspect of the present invention there is therefore provided a switched capacitor digital-to-analogue converter (DAC) comprising an active circuit with a feedback element, the feedback element comprising a feedback capacitor, a second capacitor and a switch to connect the second capacitor to one of first and second references to store charge on the second capacitor and to connect the second capacitor in parallel with the feedback capacitor to share said stored charge with the feedback capacitor; wherein the switch is further configured to connect the second capacitor to a substantially signal-independent reference prior to connection of the second capacitor to said one of said first and second references.
Connecting the second capacitor to a substantially signal-independent reference before connecting it to one of the first and second references allows signal-dependent charges to flow onto or off the second capacitor before the capacitor is recharged. In other words the charge on the second capacitor may be brought to a substantially signal-independent or predetermined state of charge prior to its connection to one of the first and second references, so that there is little or no signal-dependent loading of these references. Generally the first and second references will comprise reference voltage sources although other forms of reference, may also be employed; they may be derived from a single reference.
The signal-independent reference may comprise an additional reference voltage source or, in a differential DAC, may be derived by averaging voltages from the two mirrored halves of the differential circuitry. This may be accomplished in a relatively simple manner by providing means to connect second capacitors of the positive and negative voltage generating portions of the differential DAC. Where one end of the second capacitors is effectively at a virtual earth one or more switches may be provided to short the live or output ends of the second capacitors together to allow the charges on these to be shared, resulting in a substantially signal-independent average charge on both these second capacitors.
In such a differential DAC first and second active circuits may be used to generate first and second analogue output voltages of substantially equal magnitude but opposite polarity with respect to another voltage, typically ground. Either one or both outputs from such a differential DAC may be used in later processing.
The digital-to-analogue converter may include a third capacitor to provide multi-bit conversion and, in this case, the third capacitor may also be connected to the same or another substantially signal-independent reference. Advantageously, particularly in such a multi-bit DAC, the switching may be simplified by providing means to selectively connect the second capacitor to one of two drive lines and means to selectively connect each of these drive lines to either the first or the second reference or to a substantially signal-independent reference. This latter may be accomplished by shorting the drive lines together.
In a related aspect the invention provides a feedback element for a switched capacitor DAC comprising a feedback capacitor, a second capacitor, a switch; and a clock generator, and wherein the clock generator is configured to control the switch to connect the second capacitor to one of first and second references to store charge on the second capacitor and to connect the second capacitor in parallel with the feedback capacitor to share said stored charge with the feedback capacitor, and wherein the clock generator is further configured to connect the second capacitor to a substantially signal-independent reference prior to connection of the second capacitor to said one of said first and second references.
This feedback element may be employed as a gain control element in a digital-to-analogue converter as described above.
According to a further aspect there is provided a switched capacitor digital-to-analogue converter in which a switched capacitor is repetitively and selectively connected to a positive and to a negative reference voltage and to a charge storage capacitor to controllably share charge with the charge storage capacitor, the digital-to-analogue converter further comprising switch means for bringing the charge on the switched capacitor to a substantially predetermined state before said connection of the switched capacitor to a said reference voltage.